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Author	SHA1	Message	Date
ixgbe	307772fcda	readme : add RVV,ZVFH,ZFH,ZICBOP support for RISC-V (#17259) ... Signed-off-by: Wang Yang <yangwang@iscas.ac.cn>	2025-11-14 09:12:56 +02:00
ixgbe	1215dde7b0	ggml-cpu : add RISC-V vector intrinsic support for silu and cvar operations (#17227) ... Signed-off-by: Wang Yang <yangwang@iscas.ac.cn>	2025-11-13 13:13:32 +01:00
ixgbe	ca4844062b	ggml-cpu : add RISC-V RVV (Zvfh) optimization for FP16 to FP32 conversion (#17161) ... Signed-off-by: Wang Yang <yangwang@iscas.ac.cn>	2025-11-11 13:41:51 +02:00