Jeff Bolz
c9ca51c1f6
* vulkan: combine duplicated fastdiv functions, rename the one optimizing small divs * remove one more fastdiv
425 lines
16 KiB
Plaintext
425 lines
16 KiB
Plaintext
#version 450
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#extension GL_EXT_control_flow_attributes : enable
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#ifdef COOPMAT2
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#extension GL_NV_cooperative_matrix2 : enable
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#extension GL_EXT_shader_explicit_arithmetic_types_float16 : require
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#extension GL_KHR_memory_scope_semantics : enable
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#endif
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#ifdef COOPMAT
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#extension GL_KHR_cooperative_matrix : enable
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#extension GL_KHR_shader_subgroup_basic : enable
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#extension GL_EXT_shader_explicit_arithmetic_types_float16 : require
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#extension GL_KHR_memory_scope_semantics : enable
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#endif
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#include "types.glsl"
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#include "utils.glsl"
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// shape notation: [dim(N), ..., dim(0)] -- stride(dim(j)) >= stride(dim(i)) if i > j
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layout(binding = 0) readonly buffer A {
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A_TYPE knl_data[];
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}; // src0 - kernel: [KW, KH, KD, IC*OC]
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layout(binding = 1) readonly buffer B {
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B_TYPE src_data[];
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}; // src1 - input: [IW, IH, ID, IC*N] -- channel_first format
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layout(binding = 2) writeonly buffer D {
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D_TYPE dst_data[];
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}; // dst - result: [OW, OH, OD, OC*N]
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layout(push_constant) uniform parameter {
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// I/O channels, batch size
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uint32_t OC;
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uint32_t IC;
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uint32_t N;
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// Tensor spatial sizes: input, output
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uint32_t IW;
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uint32_t IH;
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uint32_t ID;
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uint32_t OW;
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uint32_t OH;
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uint32_t OD;
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// Strides in elements
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uint32_t nb01;
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uint32_t nb02;
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uint32_t nb03;
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uint32_t nb11;
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uint32_t nb12;
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uint32_t nb13;
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uint32_t nb1;
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uint32_t nb2;
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uint32_t nb3;
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// fastdiv helper values
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uint32_t OWmp; uint32_t OWL;
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uint32_t OWOHmp; uint32_t OWOHL;
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uint32_t OWOHODmp; uint32_t OWOHODL;
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}
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p;
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layout(local_size_x_id = 0, local_size_y = 1, local_size_z = 1) in;
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// Blocktile sizes
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layout(constant_id = 1) const uint BS_K = 128;
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layout(constant_id = 2) const uint BS_CRS = 16;
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layout(constant_id = 3) const uint BS_NPQ = 128;
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// Thread-tile sizes
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layout(constant_id = 4) const uint TS_K = 8;
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layout(constant_id = 5) const uint SHMEM_PAD = 4;
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// Stride, padding, dilation
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layout(constant_id = 6) const uint s0 = 1;
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layout(constant_id = 7) const uint s1 = 1;
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layout(constant_id = 8) const uint s2 = 1;
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layout(constant_id = 9) const uint p0 = 0;
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layout(constant_id = 10) const uint p1 = 0;
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layout(constant_id = 11) const uint p2 = 0;
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layout(constant_id = 12) const uint d0 = 1;
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layout(constant_id = 13) const uint d1 = 1;
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layout(constant_id = 14) const uint d2 = 1;
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// Kernel spatial sizes
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layout(constant_id = 15) const uint KW = 1;
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layout(constant_id = 16) const uint KH = 1;
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layout(constant_id = 17) const uint KD = 1;
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// when set, skip bounds checks and address clamps (K/CRS/NPQ are tile-aligned)
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layout(constant_id = 18) const uint aligned = 0;
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// stage cm2 result through shmem (Csh) for coalesced stores. cm1 always does this.
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layout(constant_id = 19) const uint csh_store = 0;
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#ifdef COOPMAT
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// cm1 subgroup tile: each subgroup computes a WM x WN region as a grid of
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// TM x TN x TK fragments. Requires WM%TM == WN%TN == BS_K%WM == BS_NPQ%WN ==
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// BS_CRS%TK == 0, and WG_SIZE == (BS_K/WM) * (BS_NPQ/WN) * subgroup_size.
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layout(constant_id = 20) const uint WM = 32;
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layout(constant_id = 21) const uint WN = 32;
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const uint TM = 16;
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const uint TN = 16;
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const uint TK = 16;
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const uint cms_per_row = WM / TM;
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const uint cms_per_col = WN / TN;
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const uint warps_M = BS_K / WM;
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const uint warps_N = BS_NPQ / WN;
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#endif
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// without padding, ID_idx/IH_idx/IW_idx are in bounds by construction
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const bool dhw_in_bounds = (p0 == 0) && (p1 == 0) && (p2 == 0);
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uint32_t tid = gl_LocalInvocationID.x;
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const uint32_t WG_SIZE = gl_WorkGroupSize.x;
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uint splitWork(uint work_size, uint block_size) {
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return (block_size + work_size - 1) / block_size;
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}
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uint32_t K = p.OC;
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uint32_t CRS = p.IC * KD * KH * KW;
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uint32_t NPQ = p.N * p.OD * p.OH * p.OW;
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// Number of blocktiles per input
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uint32_t NB_CRS = splitWork(CRS, BS_CRS);
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#if defined(COOPMAT2) || defined(COOPMAT)
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#define SHMEM_TYPE float16_t
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#else
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#define SHMEM_TYPE float
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#endif
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const uint32_t Ash_stride = BS_CRS + SHMEM_PAD;
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const uint32_t Bsh_stride = BS_NPQ + SHMEM_PAD;
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const uint32_t Ash_len = BS_K * Ash_stride;
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const uint32_t Bsh_len = BS_CRS * Bsh_stride;
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shared SHMEM_TYPE Ash[Ash_len]; // K x CRS
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shared SHMEM_TYPE Bsh[Bsh_len]; // CRS x NPQ
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#if defined(COOPMAT2) || defined(COOPMAT)
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// stage matC through shmem so global stores are row-major (NPQ-contiguous)
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const uint32_t Csh_stride = BS_NPQ;
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#ifdef COOPMAT
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const uint32_t Csh_len = BS_K * Csh_stride;
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#else
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const uint32_t Csh_len = csh_store != 0 ? BS_K * Csh_stride : 8; // 8 to workaround compiler bug
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#endif
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shared SHMEM_TYPE Csh[Csh_len]; // K x NPQ
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#endif
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// Threadtile sizes
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const uint32_t TS_NPQ = BS_K * BS_NPQ / WG_SIZE / TS_K;
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// Number of threadtiles per blocktile
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const uint32_t NT_NPQ = BS_NPQ / TS_NPQ;
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/*
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Compute
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KxCRS @ CRSxNPQ = K x NPQ
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K=OC
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C=IC
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D,R,S=KD,KH,KW
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Z,P,Q=OD,OH,OW
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*/
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uint32_t B_idx_K = gl_WorkGroupID.x;
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uint32_t B_idx_NPQ = gl_WorkGroupID.y + gl_WorkGroupID.z * 512;
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uint32_t T_y = tid / NT_NPQ;
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uint32_t T_x = tid % NT_NPQ;
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uint32_t Ar = tid / BS_CRS;
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uint32_t Ac = tid % BS_CRS;
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const uint32_t ArpWg = WG_SIZE / BS_CRS;
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uint32_t Br = tid / BS_NPQ;
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uint32_t Bc = tid % BS_NPQ;
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const uint32_t BrpWg = WG_SIZE / BS_NPQ;
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void split_crs(uint32_t crs_idx, out uint32_t ic, out uint32_t kd, out uint32_t kh, out uint32_t kw) {
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const uint32_t KHKW = KH * KW;
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const uint32_t KDKHKW = KD * KHKW;
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ic = crs_idx / KDKHKW;
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uint32_t rem = crs_idx - ic * KDKHKW;
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kd = rem / KHKW;
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rem = rem - kd * KHKW;
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kh = rem / KW;
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kw = rem - kh * KW;
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}
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void split_npq(uint32_t npq_idx, out uint32_t n, out uint32_t od, out uint32_t oh, out uint32_t ow) {
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const uint32_t OWOH = p.OW * p.OH;
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n = fastdiv(npq_idx, p.OWOHODmp, p.OWOHODL);
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uint32_t rem = npq_idx - n * p.OD * OWOH;
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od = fastdiv(rem, p.OWOHmp, p.OWOHL);
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rem = rem - od * OWOH;
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oh = fastdiv(rem, p.OWmp, p.OWL);
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ow = rem - oh * p.OW;
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}
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#ifdef COOPMAT2
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#define ACC_TYPE float16_t
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ACC_TYPE perElemOpStore(const in uint32_t r, const in uint32_t c, const in ACC_TYPE elem)
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{
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uint32_t K_idx = B_idx_K * BS_K + r;
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uint32_t NPQ_idx = B_idx_NPQ * BS_NPQ + c;
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uint32_t N_idx;
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uint32_t OD_idx;
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uint32_t OH_idx;
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uint32_t OW_idx;
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split_npq(NPQ_idx, N_idx, OD_idx, OH_idx, OW_idx);
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uint32_t dst_idx = OW_idx + OH_idx * p.nb1 + OD_idx * p.nb2 + (N_idx * p.OC + K_idx) * p.nb3;
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if (aligned != 0 || (K_idx < K && NPQ_idx < NPQ)) {
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dst_data[dst_idx] = D_TYPE(elem);
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}
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return elem;
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}
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#endif
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void main() {
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if (B_idx_NPQ * BS_NPQ >= NPQ) {
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return;
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}
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#ifdef COOPMAT2
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coopmat<ACC_TYPE, gl_ScopeWorkgroup, BS_K, BS_NPQ, gl_MatrixUseAccumulator> matC;
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matC = coopmat<ACC_TYPE, gl_ScopeWorkgroup, BS_K, BS_NPQ, gl_MatrixUseAccumulator>(0.0);
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#elif defined(COOPMAT)
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coopmat<float16_t, gl_ScopeSubgroup, TM, TN, gl_MatrixUseAccumulator> sums[cms_per_row * cms_per_col];
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[[unroll]] for (uint i = 0; i < cms_per_row * cms_per_col; i++) {
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sums[i] = coopmat<float16_t, gl_ScopeSubgroup, TM, TN, gl_MatrixUseAccumulator>(0.0);
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}
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const uint warp_r = gl_SubgroupID / warps_N;
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const uint warp_c = gl_SubgroupID % warps_N;
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#else
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float regC[TS_K][TS_NPQ];
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for (uint32_t T_ly = 0; T_ly < TS_K; T_ly++) {
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for (uint32_t T_lx = 0; T_lx < TS_NPQ; T_lx++) {
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regC[T_ly][T_lx] = 0.0;
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}
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}
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#endif
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/* Advance block in CRS dim */
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[[dont_unroll]] for (uint32_t B_idx_CRS = 0; B_idx_CRS < NB_CRS; B_idx_CRS++) {
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uint32_t CRS_idx_a = B_idx_CRS * BS_CRS + Ac;
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uint32_t IC_idx_a;
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uint32_t KD_idx_a;
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uint32_t KH_idx_a;
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uint32_t KW_idx_a;
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split_crs(CRS_idx_a, IC_idx_a, KD_idx_a, KH_idx_a, KW_idx_a);
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/* Load kernel to A_block: (BS_K x BS_CRS)*/
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UNROLL for (uint32_t r_offset = 0; r_offset < BS_K; r_offset += ArpWg) {
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uint32_t B_ly = r_offset + Ar;
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uint32_t B_lx = Ac;
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uint32_t K_idx = B_idx_K * BS_K + B_ly; /* Global K_idx (row index of A)*/
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uint32_t knl_idx = KW_idx_a + KH_idx_a * p.nb01 + KD_idx_a * p.nb02 + (K_idx * p.IC + IC_idx_a) * p.nb03;
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if (aligned == 0) {
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knl_idx = min(knl_idx, K * CRS - 1);
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}
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float val = knl_data[knl_idx];
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if (aligned == 0 && (K_idx >= K || CRS_idx_a >= CRS)) {
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val = 0.0;
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}
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Ash[B_ly * Ash_stride + B_lx] = SHMEM_TYPE(val);
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}
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/* Load input to B_block: (BS_CRS x BS_NPQ) */
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UNROLL for (uint32_t r_offset = 0; r_offset < BS_CRS; r_offset += BrpWg) {
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uint32_t B_ly = r_offset + Br; /* Row index of B block */
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uint32_t B_lx = Bc;
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uint32_t NPQ_idx = B_idx_NPQ * BS_NPQ + B_lx; /* Global NPQ index (column index of B) */
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uint32_t N_idx;
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uint32_t OD_idx;
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uint32_t OH_idx;
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uint32_t OW_idx;
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split_npq(NPQ_idx, N_idx, OD_idx, OH_idx, OW_idx);
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uint32_t CRS_idx_b = B_idx_CRS * BS_CRS + B_ly;
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uint32_t IC_idx_b;
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uint32_t KD_idx_b;
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uint32_t KH_idx_b;
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uint32_t KW_idx_b;
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split_crs(CRS_idx_b, IC_idx_b, KD_idx_b, KH_idx_b, KW_idx_b);
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uint32_t ID_idx = OD_idx * s2 + KD_idx_b * d2 - p2;
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uint32_t IH_idx = OH_idx * s1 + KH_idx_b * d1 - p1;
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uint32_t IW_idx = OW_idx * s0 + KW_idx_b * d0 - p0;
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uint32_t src_idx = IW_idx + IH_idx * p.nb11 + ID_idx * p.nb12 + (N_idx * p.IC + IC_idx_b) * p.nb13;
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// skip clamp when address can't go OOB
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if (aligned == 0 || !dhw_in_bounds) {
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src_idx = min(src_idx, p.IC * p.N * p.IW * p.IH * p.ID - 1);
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}
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float val = src_data[src_idx];
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bool oob = false;
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if (aligned == 0 && (CRS_idx_b >= CRS || NPQ_idx >= NPQ)) {
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oob = true;
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}
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// also catches lower-bound underflow (idx wraps to 0x80000000+)
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if (!dhw_in_bounds && (ID_idx >= p.ID || IH_idx >= p.IH || IW_idx >= p.IW)) {
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oob = true;
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}
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if (oob) {
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val = 0.0;
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}
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Bsh[B_ly * Bsh_stride + B_lx] = SHMEM_TYPE(val);
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}
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barrier();
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#ifdef COOPMAT2
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coopmat<float16_t, gl_ScopeWorkgroup, BS_K, BS_CRS, gl_MatrixUseA> matA;
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coopmat<float16_t, gl_ScopeWorkgroup, BS_CRS, BS_NPQ, gl_MatrixUseB> matB;
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coopMatLoad(matA, Ash, 0, Ash_stride, gl_CooperativeMatrixLayoutRowMajor);
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coopMatLoad(matB, Bsh, 0, Bsh_stride, gl_CooperativeMatrixLayoutRowMajor);
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matC = coopMatMulAdd(matA, matB, matC);
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#elif defined(COOPMAT)
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// each subgroup multiplies its grid of fragments per TK-sized CRS chunk
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[[unroll]] for (uint k_step = 0; k_step < BS_CRS / TK; k_step++) {
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coopmat<float16_t, gl_ScopeSubgroup, TM, TK, gl_MatrixUseA> cache_a[cms_per_row];
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[[unroll]] for (uint cm_row = 0; cm_row < cms_per_row; cm_row++) {
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const uint a_off = (warp_r * WM + cm_row * TM) * Ash_stride + k_step * TK;
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coopMatLoad(cache_a[cm_row], Ash, a_off, Ash_stride, gl_CooperativeMatrixLayoutRowMajor);
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}
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[[unroll]] for (uint cm_col = 0; cm_col < cms_per_col; cm_col++) {
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coopmat<float16_t, gl_ScopeSubgroup, TK, TN, gl_MatrixUseB> cache_b;
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const uint b_off = k_step * TK * Bsh_stride + warp_c * WN + cm_col * TN;
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coopMatLoad(cache_b, Bsh, b_off, Bsh_stride, gl_CooperativeMatrixLayoutRowMajor);
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[[unroll]] for (uint cm_row = 0; cm_row < cms_per_row; cm_row++) {
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sums[cm_col * cms_per_row + cm_row] = coopMatMulAdd(cache_a[cm_row], cache_b, sums[cm_col * cms_per_row + cm_row]);
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}
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}
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}
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#else
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if (T_y * TS_K < K) {
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UNROLL for (uint32_t CRS_lidx = 0; CRS_lidx < BS_CRS; CRS_lidx++) {
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float regA[TS_K];
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float regB[TS_NPQ];
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for (uint32_t T_ly = 0; T_ly < TS_K; T_ly++) {
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regA[T_ly] = Ash[(T_y * TS_K + T_ly) * Ash_stride + CRS_lidx];
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}
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for (uint32_t T_lx = 0; T_lx < TS_NPQ; T_lx++) {
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regB[T_lx] = Bsh[CRS_lidx * Bsh_stride + T_x * TS_NPQ + T_lx];
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}
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for (uint32_t T_ly = 0; T_ly < TS_K; T_ly++) {
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for (uint32_t T_lx = 0; T_lx < TS_NPQ; T_lx++) {
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regC[T_ly][T_lx] = fma(regA[T_ly], regB[T_lx], regC[T_ly][T_lx]);
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}
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}
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}
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}
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#endif
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barrier();
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}
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/* Save C* */
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#if defined(COOPMAT2) || defined(COOPMAT)
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// stage matC into Csh, then write to dst with coalesced NPQ-contiguous stores
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#ifdef COOPMAT
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const bool use_staged_store = true;
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#else
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const bool use_staged_store = (csh_store != 0);
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#endif
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if (use_staged_store) {
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#ifdef COOPMAT
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// cm1: each subgroup stores its fragment grid into its Csh slot
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[[unroll]] for (uint cm_row = 0; cm_row < cms_per_row; cm_row++) {
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[[unroll]] for (uint cm_col = 0; cm_col < cms_per_col; cm_col++) {
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const uint csh_off = (warp_r * WM + cm_row * TM) * Csh_stride + warp_c * WN + cm_col * TN;
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coopMatStore(sums[cm_col * cms_per_row + cm_row], Csh, csh_off, Csh_stride, gl_CooperativeMatrixLayoutRowMajor);
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}
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}
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#else
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coopMatStore(matC, Csh, 0, Csh_stride, gl_CooperativeMatrixLayoutRowMajor);
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#endif
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barrier();
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// cooperative shmem->global: WG threads spread across BS_NPQ (the
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// contiguous direction of dst), each iter covers store_rows_per_iter K-rows
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const uint32_t store_rows_per_iter = WG_SIZE / BS_NPQ;
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const uint32_t store_iters = BS_K / store_rows_per_iter;
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const uint32_t k_thread_offset = tid / BS_NPQ;
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const uint32_t npq_thread = tid % BS_NPQ;
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[[unroll]] for (uint32_t i = 0; i < store_iters; i++) {
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uint32_t k_local = i * store_rows_per_iter + k_thread_offset;
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uint32_t K_idx = B_idx_K * BS_K + k_local;
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uint32_t NPQ_idx = B_idx_NPQ * BS_NPQ + npq_thread;
|
|
uint32_t N_idx;
|
|
uint32_t OD_idx;
|
|
uint32_t OH_idx;
|
|
uint32_t OW_idx;
|
|
split_npq(NPQ_idx, N_idx, OD_idx, OH_idx, OW_idx);
|
|
uint32_t dst_idx = OW_idx + OH_idx * p.nb1 + OD_idx * p.nb2 + (N_idx * p.OC + K_idx) * p.nb3;
|
|
if (aligned != 0 || (K_idx < K && NPQ_idx < NPQ)) {
|
|
dst_data[dst_idx] = D_TYPE(Csh[k_local * Csh_stride + npq_thread]);
|
|
}
|
|
}
|
|
}
|
|
#ifdef COOPMAT2
|
|
else {
|
|
coopMatPerElementNV(matC, matC, perElemOpStore);
|
|
}
|
|
#endif
|
|
#else
|
|
if (T_y * TS_K < K) {
|
|
for (uint32_t T_ly = 0; T_ly < TS_K; T_ly++) {
|
|
for (uint32_t T_lx = 0; T_lx < TS_NPQ; T_lx++) {
|
|
uint32_t K_idx = B_idx_K * BS_K + T_y * TS_K + T_ly;
|
|
uint32_t NPQ_idx = B_idx_NPQ * BS_NPQ + T_x * TS_NPQ + T_lx;
|
|
uint32_t N_idx;
|
|
uint32_t OD_idx;
|
|
uint32_t OH_idx;
|
|
uint32_t OW_idx;
|
|
split_npq(NPQ_idx, N_idx, OD_idx, OH_idx, OW_idx);
|
|
uint32_t dst_idx = OW_idx + OH_idx * p.nb1 + OD_idx * p.nb2 + (N_idx * p.OC + K_idx) * p.nb3;
|
|
if (aligned != 0 || (K_idx < K && NPQ_idx < NPQ)) {
|
|
dst_data[dst_idx] = D_TYPE(regC[T_ly][T_lx]);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
#endif
|
|
}
|