vulkan: make FA mask/softcap enables spec constants (#19309)
* vulkan: make FA mask/softcap enables spec constants * don't specialize for sinks * bump timeout a little bit
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@@ -127,7 +127,7 @@ void main() {
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continue;
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}
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// Only load if the block is not all zeros
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if ((p.mask_n_head_log2 & MASK_ENABLE_BIT) != 0 && mask_opt_bits != MASK_OPT_ALL_ZERO) {
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if (MASK_ENABLE && mask_opt_bits != MASK_OPT_ALL_ZERO) {
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bool nem1_bounds_check = !(p.gqa_ratio > 1) && (p.nem1 % Br) != 0;
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[[unroll]] for (uint32_t idx = 0; idx < Bc * Br; idx += gl_WorkGroupSize.x) {
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@@ -181,7 +181,7 @@ void main() {
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}
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}
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if (p.logit_softcap != 0.0f) {
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if (LOGIT_SOFTCAP) {
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[[unroll]] for (uint32_t r = 0; r < Br; ++r) {
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[[unroll]] for (uint32_t c = 0; c < cols_per_thread; ++c) {
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Sf[r][c] = p.logit_softcap * tanh(Sf[r][c]);
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@@ -189,7 +189,7 @@ void main() {
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}
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}
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if ((p.mask_n_head_log2 & MASK_ENABLE_BIT) != 0 && mask_opt_bits != MASK_OPT_ALL_ZERO) {
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if (MASK_ENABLE && mask_opt_bits != MASK_OPT_ALL_ZERO) {
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[[unroll]] for (uint32_t c = 0; c < cols_per_thread; ++c) {
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[[unroll]] for (uint32_t r = 0; r < Br; ++r) {
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float mvf = masksh[c * cols_per_iter + col_tid][r];
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@@ -10,7 +10,11 @@ layout (constant_id = 5) const uint32_t Clamp = 0;
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layout (constant_id = 6) const uint32_t D_split = 16;
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layout (constant_id = 7) const uint32_t SubGroupSize = 32;
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layout (constant_id = 8) const uint32_t K_LOAD_SHMEM = 0;
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layout (constant_id = 9) const bool USE_MASK_OPT = false;
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layout (constant_id = 9) const uint32_t Flags = 0;
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const bool USE_MASK_OPT = (Flags & 1) != 0;
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const bool MASK_ENABLE = (Flags & 2) != 0;
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const bool LOGIT_SOFTCAP = (Flags & 4) != 0;
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// Round up head sizes to a multiple of 16, for coopmat1/coopmat2 paths
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const uint32_t HSK_pad = (HSK + 15) & ~15;
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@@ -60,7 +64,6 @@ layout (push_constant) uniform parameter {
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} p;
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#define SINK_ENABLE_BIT (1<<24)
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#define MASK_ENABLE_BIT (1<<16)
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#define N_LOG2_MASK 0xFFFF
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layout (binding = 4) readonly buffer S {float data_s[];};
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@@ -160,7 +160,7 @@ void main() {
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mask_cache[idx] = f16vec4(0);
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}
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if ((p.mask_n_head_log2 & MASK_ENABLE_BIT) != 0) {
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if (MASK_ENABLE) {
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if (USE_MASK_OPT && mask_opt_idx != j / 16) {
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mask_opt_idx = j / 16;
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@@ -303,7 +303,7 @@ void main() {
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coopMatStore(SfMat, sfsh, coord, sfshstride, gl_CooperativeMatrixLayoutRowMajor);
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barrier();
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if (p.logit_softcap != 0.0f) {
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if (LOGIT_SOFTCAP) {
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[[unroll]] for (uint32_t idx = 0; idx < Bc * Br / 4; idx += gl_WorkGroupSize.x) {
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uint32_t c = (idx + tid) / (Br / 4);
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uint32_t r = (idx + tid) % (Br / 4);
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@@ -314,7 +314,7 @@ void main() {
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barrier();
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}
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if ((p.mask_n_head_log2 & MASK_ENABLE_BIT) != 0) {
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if (MASK_ENABLE) {
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[[unroll]] for (uint32_t idx = 0; idx < Bc * Br / 4; idx += gl_WorkGroupSize.x) {
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uint32_t c = (idx + tid) / (Br / 4);
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uint32_t r = (idx + tid) % (Br / 4);
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@@ -155,7 +155,7 @@ void main() {
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for (uint32_t j = start_j; j < end_j; ++j) {
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coopmat<float16_t, gl_ScopeWorkgroup, Br, Bc, gl_MatrixUseAccumulator> mv = coopmat<float16_t, gl_ScopeWorkgroup, Br, Bc, gl_MatrixUseAccumulator>(0);
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if ((p.mask_n_head_log2 & MASK_ENABLE_BIT) != 0) {
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if (MASK_ENABLE) {
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if (USE_MASK_OPT && mask_opt_idx != j / 16) {
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mask_opt_idx = j / 16;
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@@ -197,14 +197,14 @@ void main() {
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coopMatLoadTensorNV(K_T, data_k, k_offset, sliceTensorLayoutNV(tensorLayoutK, j * Bc, Bc, 0, HSK_pad), tensorViewTranspose DECODEFUNC);
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S = coopMatMulAdd(Qf16, K_T, S);
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if (p.logit_softcap != 0.0f) {
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if (LOGIT_SOFTCAP) {
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[[unroll]]
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for (int k = 0; k < S.length(); ++k) {
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S[k] = ACC_TYPE(p.logit_softcap)*tanh(S[k]);
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}
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}
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if ((p.mask_n_head_log2 & MASK_ENABLE_BIT) != 0) {
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if (MASK_ENABLE) {
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S += slopeMat*coopmat<ACC_TYPE, gl_ScopeWorkgroup, Br, Bc, gl_MatrixUseAccumulator>(mv);
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}
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