CUDA: tighter MMQ src1 buffer size for native fp4 (#25613)
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@@ -21,6 +21,9 @@ enum mmq_q8_1_ds_layout {
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MMQ_Q8_1_DS_LAYOUT_D2S6,
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};
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static constexpr int QK8_1_MMQ = 4*QK8_1;
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static constexpr int QK_FP4_MMQ = 2*QK8_1_MMQ;
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struct block_q8_1_mmq {
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// The y float data is converted to a data layout that can simply be copied to shared memory as a contiguous block.
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// The y float data is first grouped as blocks of 128 values.
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@@ -39,7 +42,7 @@ struct block_q8_1_mmq {
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half d2s6[8]; // 1 16 bit scale per 64 values + 1 16 bit partial sum per 16 values for the first 96 values,
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// stored as d0,d1,s1,s2,s3,s4,s5
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};
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int8_t qs[4*QK8_1]; // 128 values quantized to 8 bit each
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int8_t qs[QK8_1_MMQ];
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};
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// this struct is used for fp4 data types (currently only used for Blackwell)
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@@ -47,10 +50,10 @@ struct block_q8_1_mmq {
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// nvfp4 has block size 16, each int32 of d4 contains 4 ue4m3 scales
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struct block_fp4_mmq {
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uint32_t d4[4];
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int8_t qs[4 * 32]; // 256 FP4 values packed as 4-bit pairs (2 per byte)
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int8_t qs[QK_FP4_MMQ / 2];
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};
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static_assert(sizeof(block_q8_1_mmq) == 4*QK8_1 + 4*sizeof(half2), "Unexpected block_q8_1_mmq size");
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static_assert(sizeof(block_q8_1_mmq) == QK8_1_MMQ + 4*sizeof(half2), "Unexpected block_q8_1_mmq size");
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static_assert(sizeof(block_q8_1_mmq) == 4*sizeof(block_q8_1), "Unexpected block_q8_1_mmq size");
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static_assert(sizeof(block_fp4_mmq) == sizeof(block_q8_1_mmq), "Unexpected block_fp4_mmq size");
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@@ -833,9 +836,9 @@ static __device__ __forceinline__ void mul_mat_q_process_tile(
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#if defined(BLACKWELL_MMA_AVAILABLE)
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// FP4 tile stores 8 blocks
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constexpr int ne_block = (type == GGML_TYPE_MXFP4 || type == GGML_TYPE_NVFP4) ? QK_K : 4 * QK8_1;
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constexpr int ne_block = (type == GGML_TYPE_MXFP4 || type == GGML_TYPE_NVFP4) ? QK_FP4_MMQ : QK8_1_MMQ;
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#else
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constexpr int ne_block = 4 * QK8_1;
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constexpr int ne_block = QK8_1_MMQ;
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#endif // defined(BLACKWELL_MMA_AVAILABLE)
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constexpr int ITER_K = ggml_cuda_mmq_get_K_vram(type, J, fallback);
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