metal : per-device tuned (Q, NE) for flash-attn vec (#26570)
* metal : per-device tuned (Q, NE) for flash-attn vec (#25750) * rebase Q-generic FA vec body from 01dc93607 (#23114) * add 53 f16 (Q,NE) flash-attn vec instantiations (vec 80 -> 133) * add FA vec (Q,NE) tuning table + dispatch wiring + SMEM cap fallback * add FA vec (Q,NE) perf sweep * fill tuning result * fold family table into a per-family representative SKU * refactor tuning result format * extend FA vec tuning to quantized KV caches * sync fa vec tuner bucketing with runtime, use pointwise tuning regret * update tuned table * format and cleanup * prefix fa_vec tuning procs with ggml_backend_metal_tuning_, drop unused fa_vec_override_active * add device id -> token lookup for the offline tuning tool * add ggml-metal-tuning skeleton * add op-agnostic perf cell + median timing for the tuner * add FA-vec graph build + tensor init to the tuner * tools : add FA-vec (Q,NE) sweep, compression and table emit * cool down and re-measure the dirty window on thermal drift * test-backend-ops : replace the FA vec tune mode with a bounded (Q,NE) slice * tools : document the Metal tuner, point the table comment at it * abort on unknown KV type, single-source fa_vec_legal_ne * cleanup * honor -o in the FA vec (Q,NE) slice * retune FA-vec (Q, NE) under a pointwise no-harm gate * cont : add fa-vec tunings for M1 Pro, M2 Ultra, M5 Max --------- Co-authored-by: Georgi Gerganov <ggerganov@gmail.com>
This commit is contained in:
co-authored by
Georgi Gerganov
parent
b615f5b4bd
commit
f280b26983
@@ -7,6 +7,7 @@
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#include "ggml-metal-impl.h"
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#include "ggml-metal-common.h"
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#include "ggml-metal-device.h"
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#include "ggml-metal-tuning.h"
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#include <cassert>
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#include <algorithm>
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@@ -3346,12 +3347,18 @@ int ggml_metal_op_flash_attn_ext(ggml_metal_op_t ctx, int idx) {
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#undef FATTN_SMEM
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} else {
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// half4x4 kernel
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const int nqptg = OP_FLASH_ATTN_EXT_VEC_NQPSG; // queries per threadgroup
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auto cfg = ggml_metal_tuning::fa_vec_pick(
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props_dev->device_id,
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props_dev->gpu_family,
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(int) op->src[1]->type,
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(int) ne00, (int) ne20, // dk, dv (ne00 == dk for FA)
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ne11, ne01);
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int nqptg = cfg.Q; // queries per threadgroup
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const int ncpsg = OP_FLASH_ATTN_EXT_VEC_NCPSG; // cache values per simdgroup !! sync with kernel template arguments !!
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const int nhptg = 1; // heads per threadgroup
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GGML_ASSERT(nqptg <= 32);
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GGML_ASSERT(nqptg % 1 == 0);
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GGML_ASSERT(nqptg == 1 || nqptg == 2 || nqptg == 4); // only instantiated Q values
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GGML_ASSERT(ncpsg % 32 == 0);
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bool need_sync = false;
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@@ -3410,7 +3417,7 @@ int ggml_metal_op_flash_attn_ext(ggml_metal_op_t ctx, int idx) {
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// ne20*(nsg)
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// each simdgroup has a full f32 head vector in shared mem to accumulate results
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//
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#define FATTN_SMEM(nsg) (GGML_PAD(((GGML_PAD(ne00, 128) + 4*ncpsg + 2*GGML_PAD(ne20, 128))*(nsg))*(sizeof(float)/2), 16))
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#define FATTN_SMEM(nsg) (GGML_PAD(((GGML_PAD(ne00, 128) + 4*ncpsg + 2*GGML_PAD(ne20, 128))*(nsg)*nqptg)*(sizeof(float)/2), 16))
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int64_t nsg = 1;
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@@ -3430,6 +3437,12 @@ int ggml_metal_op_flash_attn_ext(ggml_metal_op_t ctx, int idx) {
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}
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}
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// fall back to baseline (Q=1) if the tuned config exceeds threadgroup memory
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if ((size_t) FATTN_SMEM(nsg) > props_dev->max_theadgroup_memory_size) {
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cfg = ggml_metal_tuning::fa_vec_baseline_cfg((int) ne00, (int) ne20);
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nqptg = cfg.Q; // = 1
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}
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const int32_t ns10 = nb11_attn/nb10_attn;
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const int32_t ns20 = nb21_attn/nb20_attn;
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@@ -3468,7 +3481,7 @@ int ggml_metal_op_flash_attn_ext(ggml_metal_op_t ctx, int idx) {
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/*.logit_softcap =*/ logit_softcap,
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};
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auto pipeline = ggml_metal_library_get_pipeline_flash_attn_ext_vec(lib, op, has_mask, has_sinks, has_bias, has_scap, has_kvpad, nsg, nwg, use_kv_f16, ns10, ns20);
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auto pipeline = ggml_metal_library_get_pipeline_flash_attn_ext_vec(lib, op, has_mask, has_sinks, has_bias, has_scap, has_kvpad, nqptg, cfg.NE, nsg, nwg, use_kv_f16, ns10, ns20);
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GGML_ASSERT(nsg*32 <= ggml_metal_pipeline_max_theads_per_threadgroup(pipeline));
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