sycl : support MUL_MAT and OUT_PROD with Q1_0 (#24721)
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@@ -1423,6 +1423,50 @@ static void dequantize_mul_mat_vec_q4_0_sycl(const void *vx, const dfloat *y,
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}
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}
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static void dequantize_mul_mat_vec_q1_0_sycl_reorder(const void *vx, const dfloat *y,
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float *dst, const int ncols,
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const int nrows,
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dpct::queue_ptr stream) {
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GGML_ASSERT(ncols % GGML_SYCL_DMMV_X == 0);
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const int block_num_y = (nrows + GGML_SYCL_MMV_Y - 1) / GGML_SYCL_MMV_Y;
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// the number of rows may exceed maximum grid size in the y or z dimensions, use the x dimension instead
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const sycl::range<3> block_nums(1, 1, block_num_y);
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const sycl::range<3> block_dims(1, GGML_SYCL_MMV_Y, WARP_SIZE);
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{
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dpct::has_capability_or_fail(stream->get_device(),
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{sycl::aspect::fp16});
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stream->parallel_for(
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sycl::nd_range<3>(block_nums * block_dims, block_dims),
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[=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] {
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dequantize_mul_mat_vec_reorder<QK1_0, QR1_0, dequantize_q1_0_reorder>(
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vx, y, dst, ncols, nrows, item_ct1);
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});
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}
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}
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static void dequantize_mul_mat_vec_q1_0_sycl(const void *vx, const dfloat *y,
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float *dst, const int ncols,
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const int nrows,
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dpct::queue_ptr stream) {
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GGML_ASSERT(ncols % GGML_SYCL_DMMV_X == 0);
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const int block_num_y = (nrows + GGML_SYCL_MMV_Y - 1) / GGML_SYCL_MMV_Y;
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// the number of rows may exceed maximum grid size in the y or z dimensions, use the x dimension instead
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const sycl::range<3> block_nums(1, 1, block_num_y);
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const sycl::range<3> block_dims(1, GGML_SYCL_MMV_Y, WARP_SIZE);
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{
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dpct::has_capability_or_fail(stream->get_device(),
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{sycl::aspect::fp16});
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stream->parallel_for(
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sycl::nd_range<3>(block_nums * block_dims, block_dims),
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[=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] {
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dequantize_mul_mat_vec<QK1_0, QR1_0, dequantize_q1_0>(
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vx, y, dst, ncols, nrows, item_ct1);
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});
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}
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}
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static void dequantize_mul_mat_vec_q4_1_sycl(const void *vx, const dfloat *y,
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float *dst, const int ncols,
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const int nrows,
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@@ -1759,6 +1803,7 @@ void ggml_sycl_op_dequantize_mul_mat_vec(
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sycl::half *src1_dfloat = nullptr; // dfloat == half
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bool src1_convert_f16 =
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src0->type == GGML_TYPE_Q1_0 ||
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src0->type == GGML_TYPE_Q4_0 || src0->type == GGML_TYPE_Q4_1 ||
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src0->type == GGML_TYPE_Q5_0 || src0->type == GGML_TYPE_Q5_1 ||
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src0->type == GGML_TYPE_Q8_0 || src0->type == GGML_TYPE_F16 ||
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@@ -1777,6 +1822,14 @@ void ggml_sycl_op_dequantize_mul_mat_vec(
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#endif // GGML_SYCL_F16
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switch (src0->type) {
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case GGML_TYPE_Q1_0:
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if ((ggml_tensor_extra_gpu*)dst->src[0]->extra &&
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((ggml_tensor_extra_gpu*)dst->src[0]->extra)->optimized_feature.reorder) {
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dequantize_mul_mat_vec_q1_0_sycl_reorder(src0_dd_i, src1_dfloat, dst_dd_i, ne00, row_diff, stream);
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} else {
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dequantize_mul_mat_vec_q1_0_sycl(src0_dd_i, src1_dfloat, dst_dd_i, ne00, row_diff, stream);
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}
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break;
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case GGML_TYPE_Q4_0:
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if ((ggml_tensor_extra_gpu*)dst->src[0]->extra &&
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((ggml_tensor_extra_gpu*)dst->src[0]->extra)->optimized_feature.reorder) {
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