llama : enable chunked fused GDN path (#20340)
* llama : enable chunked fused GDN path * models : avoid Q and K repeats when using fused GDA * cont : fix comment Co-authored-by: Aman Gupta <amangupta052@gmail.com> * cont : fix the fix Co-authored-by: Aman Gupta <amangupta052@gmail.com> * cont : fix * metal : add GDN kernel (#20361) * metal : add Metal backend for GGML_OP_GATED_DELTA_NET Add a fused Metal kernel for the gated delta net recurrence op (#19504), enabling GPU-accelerated inference for DeltaNet-based models (Qwen3.5, etc.) on Apple Silicon. Supports both GDA (scalar gate) and KDA (per-row gate) modes with head_size 64 and 128. Unsupported configurations (head_size 32, non-contiguous tensors) gracefully fall back to CPU. Performance: Qwen3.5-0.8B Q4_K_M on M4 Max tg128: 170 -> 213 t/s (+25%) Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com> * metal : validate contiguity of all input tensors in supports_op Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com> * metal : add algorithm equivalence comment for GDA decay path Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com> * cont : unslop + optimize * cont : clean-up --------- Co-authored-by: Paul Flynn <paul@arkavo.com> Co-authored-by: Claude Opus 4.6 <noreply@anthropic.com> * CUDA: AR gated delta net improvements (#20391) * Add FastDiv to gated_delta_net_cuda * Shard columns across warps This reduces register pressure (avoids spill for S_v = 128) and gives the warp-scheduler more CTAs to schedule (thus hiding data-access latencies). * Remove unneded include in gated_delta_net.cu * Improve comments * Apply code-formating * Make sharding HIP-compatible 1. Use ggml_cuda_get_physical_warp_size() to determine warp size flexibly 2. Add test with partial warp to test sum reduction on CUDA * Remove fastdiv_s64, as we can treat neqk1 and rq3 as uint32_t * Rename variables * Enable GDN also for prefill, move TODO for chunked_GDN * Actually remove the TODO from 206890897546bd16602c3b79394fd5ea09ef199f * Get warp size at runtime warp_size is not known at compile time in hip host code. * Don't expose ggml_cuda_get_physical_warp_size on host --------- Co-authored-by: uvos <devnull@uvos.xyz> * llama : refactor llm_build_delta_net_base API --------- Co-authored-by: Aman Gupta <amangupta052@gmail.com> Co-authored-by: Paul Flynn <paul@arkavo.com> Co-authored-by: Claude Opus 4.6 <noreply@anthropic.com> Co-authored-by: Oliver Simons <osimons@nvidia.com> Co-authored-by: uvos <devnull@uvos.xyz>
This commit is contained in:
co-authored by
uvos
Aman Gupta
Paul Flynn
Claude Opus 4.6
Oliver Simons
parent
f90bd1dd84
commit
d28961d81e
@@ -84,6 +84,7 @@
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#define FC_BIN 1300
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#define FC_SUM_ROWS 1400
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#define FC_UPSCALE 1500
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#define FC_GATED_DELTA_NET 1600
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// op-specific constants
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#define OP_FLASH_ATTN_EXT_NQPSG 8
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@@ -793,6 +794,44 @@ typedef struct {
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uint64_t nb0;
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} ggml_metal_kargs_ssm_scan;
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typedef struct {
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int32_t ne00;
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int32_t ne01;
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int32_t ne02;
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int32_t ne03;
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uint64_t nb00;
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uint64_t nb01;
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uint64_t nb02;
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uint64_t nb03;
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int32_t ne10;
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int32_t ne11;
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int32_t ne12;
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int32_t ne13;
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uint64_t nb10;
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uint64_t nb11;
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uint64_t nb12;
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uint64_t nb13;
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int32_t ne20;
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int32_t ne21;
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int32_t ne22;
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int32_t ne23;
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uint64_t nb20;
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uint64_t nb21;
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uint64_t nb22;
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uint64_t nb23;
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int32_t ns02;
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int32_t ns12;
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int32_t ns22;
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int32_t ne0;
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int32_t ne1;
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int32_t ne2;
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int32_t ne3;
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uint64_t nb0;
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uint64_t nb1;
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uint64_t nb2;
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uint64_t nb3;
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} ggml_metal_kargs_gated_delta_net;
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typedef struct {
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int32_t ne00;
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int32_t ne01;
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