hexagon: improved Op queuing, buffer and cache management (#21705)
* hexagon: introduce op request batching and rewrite buffer managment The host now prepares batches of requests and dispatches them via a single dspqueue message. Buffers are mapped explicitly by NPU while processing batches. * hex-dma: disable l2 bypass since to work around new issue due to no flushes between Ops * hex-utils: add explicit l2flush and l2clear helpers * hex-opreq: use fine-grain per tensor l2 management * hex-opreq: avoid redundant invalidates for tensors we already flushed * hex-opreq: update debug messages * htp-opreq: reuse ops_context * hex-opreq: do not flush or invalidate cache lines beyond buffer boundry * hex-opreq: fix errors in log message * Revert "hex-opreq: do not flush or invalidate cache lines beyond buffer boundry" This reverts commit 8b7f0a55a750a6430ce4eb1874c7feb3d720056d. * hexagon: limit l2 flushes to 1MB which covers l2 cache * hex-opreq: limit cache flush to 4MB Looks like 4MB cont. vitual space should cover the 1MB cache. * hexagon: drop cache flush size to 2MB * hex-opreq: start reworking opreq packing * hex-opreq: introduce new way of packing opbatch where tensors are stored separately * hex-opreq: add a simple fastrpc call to force unmap all buffers * hex-l2flush: somehow 2MB does not seem robust, also cleanup step size to use line-size * hex-opreq: bump opreq batch size to 256 * hex-mm: place src1 spad at the top of vtcm for easy reuse * hex-ops: introduce internal types and disable src1 reuse for now Nothing new just formalizing the repack / qyn.quant types we've been using. * htp-opreq: use tensor pointers instead of copies * hex-opreq: introduce more robust way for tracking vtcm/spad reuse This removes the SKIP_QUANTIZE flag that became fragile with the addition of HMX and other ops. * hex-cumsum: fix error post opreq merge * hex-opreq: move request batch handling into the session Prepping everything for using dspqueue buffers and doing that inside the session is much cleaner. * hex-mm: yet another fix for src1 reuse when we're mixing hmx/hvx * hex-bufs: introduce pinned mmapings and use non-pinned ones for model buffers * hex-buf: add support for allocating shared/pinned buffer for opreqs * hex-opbatch: make opbatches configurable * hex-naming: better name for ggml_hexagon_shared_buffer * hex-naming: add session->c_name() helper * hex-opbatch: start using shm but still copy for now * hex-opbatch: use shared buffer for packing opbatch * hex-opbatch: beter naming for opbatch related classes and code * hex-opbatch: reuse batched tensors with same data/dims/strides * hex-opbatch: update logging * hex-opbatch: add support for vmem limit for op batching * hex-opbatch: update htp side to properly support dynamic mmap/unmap * hex-opbatch: add OB and OQ params for run-completion script and fix the asserts in batch processing * hex-opbatch: fixed src1 handling in act ops * hex-act: fix empty src1 handling in swiglu and friends Simplify preamble macro while at it * hex-mm: minor fix vtcm and dma handling in matmul cleaning up some left-overs from merges * hex-opbatch: allocate extra 1KB for dspqueue overhead * hexagon: fix softmax for non-aligned tensors and cleanup vtcm alloc * hex-mm: properly handle hmx_disabled flag * hex-ops: update comments * hex-ops: add debug output for get/set-rows * hex-mmap: optimize un/mapping of buffers * hex-opreq: global cache flush and invalidate beyond 128KB threshold * hex-ops: add super simple opfilter regex for debugging If an Op matches the regex hex backend will reject it. * hex-opbatch: wireup newer ops missed in merge and update main switch to detect this in future * hexagon: improved vtcm acquision to remove inter-op overhead Fully compatible with QNN-HTP coex * hex-mm: fixed hvx fallback path * hex-mm: lower the vmem threshold a bit further to ~3GB * hexagon: update debug & error logs This also fixes an issue with newer llvm merging repack and non-repack functions. We use those pointer to distinguish between buffer types. * hexagon: move ops context into main context Just a cleanup. We don't need separate contexts at this point. * hex-opbatch: cleanup naming and headers for opbatch and related descriptors * hex-fa: it's now better to enable FA during TG to reduce graph splits * hexagon: remove GGML_HEXAGON_EXPERIMENTAL env var It's no longer useful. Please use more flexible GGML_HEXAGON_OPFILTER to disable Ops if needed for debugging or validation. * hexagon: fixed editorconfig check * Update ggml/src/ggml-hexagon/ggml-hexagon.cpp Co-authored-by: Sigbjørn Skjæret <sigbjorn.skjaeret@scala.com> --------- Co-authored-by: Trivikram Reddy <tamarnat@qti.qualcomm.com> Co-authored-by: Sigbjørn Skjæret <sigbjorn.skjaeret@scala.com>
This commit is contained in:
co-authored by
Sigbjørn Skjæret
Trivikram Reddy
parent
3fc65063d9
commit
9aa2807769
@@ -11,7 +11,7 @@
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#define GGML_COMMON_DECL_C
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#include "ggml-common.h"
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#include "htp-ctx.h"
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#include "htp-msg.h"
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#include "htp-ops.h"
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#include "htp-ops.h"
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#include "hvx-utils.h"
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@@ -23,27 +23,33 @@ struct get_rows_context {
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};
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#define get_rows_preamble \
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const uint32_t ne00 = octx->src0.ne[0]; \
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const uint32_t ne01 = octx->src0.ne[1]; \
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const uint32_t ne02 = octx->src0.ne[2]; \
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const uint32_t ne03 = octx->src0.ne[3]; \
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\
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const uint32_t ne10 = octx->src1.ne[0]; \
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const uint32_t ne11 = octx->src1.ne[1]; \
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const uint32_t ne12 = octx->src1.ne[2]; \
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\
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const uint32_t nb01 = octx->src0.nb[1]; \
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const uint32_t nb02 = octx->src0.nb[2]; \
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const uint32_t nb03 = octx->src0.nb[3]; \
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\
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const uint32_t nb10 = octx->src1.nb[0]; \
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const uint32_t nb11 = octx->src1.nb[1]; \
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const uint32_t nb12 = octx->src1.nb[2]; \
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\
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const uint32_t nb1 = octx->dst.nb[1]; \
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const uint32_t nb2 = octx->dst.nb[2]; \
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const uint32_t nb3 = octx->dst.nb[3]; \
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\
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const uint32_t ne00 = octx->src[0]->ne[0]; \
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const uint32_t ne01 = octx->src[0]->ne[1]; \
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const uint32_t ne02 = octx->src[0]->ne[2]; \
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const uint32_t ne03 = octx->src[0]->ne[3]; \
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\
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const uint32_t ne10 = octx->src[1]->ne[0]; \
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const uint32_t ne11 = octx->src[1]->ne[1]; \
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const uint32_t ne12 = octx->src[1]->ne[2]; \
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const uint32_t ne13 = octx->src[1]->ne[3]; \
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\
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const uint32_t ne0 = octx->dst->ne[0]; \
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const uint32_t ne1 = octx->dst->ne[1]; \
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const uint32_t ne2 = octx->dst->ne[2]; \
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const uint32_t ne3 = octx->dst->ne[3]; \
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\
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const uint32_t nb01 = octx->src[0]->nb[1]; \
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const uint32_t nb02 = octx->src[0]->nb[2]; \
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const uint32_t nb03 = octx->src[0]->nb[3]; \
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\
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const uint32_t nb10 = octx->src[1]->nb[0]; \
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const uint32_t nb11 = octx->src[1]->nb[1]; \
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const uint32_t nb12 = octx->src[1]->nb[2]; \
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\
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const uint32_t nb1 = octx->dst->nb[1]; \
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const uint32_t nb2 = octx->dst->nb[2]; \
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const uint32_t nb3 = octx->dst->nb[3]; \
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\
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const uint32_t nr = ne10 * ne11 * ne12;
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static void get_rows_thread_f32_f32(unsigned int nth, unsigned int ith, void *data) {
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@@ -51,12 +57,14 @@ static void get_rows_thread_f32_f32(unsigned int nth, unsigned int ith, void *da
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struct htp_ops_context * octx = grctx->octx;
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get_rows_preamble;
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uint64_t qt = HAP_perf_get_qtimer_count();
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// parallelize by src1 elements (which correspond to dst rows)
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const uint32_t dr = grctx->src1_nrows_per_thread;
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const uint32_t ir0 = dr * ith;
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const uint32_t ir1 = (ir0 + dr < nr) ? (ir0 + dr) : nr;
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const bool is_i32 = (octx->src1.type == HTP_TYPE_I32);
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const bool is_i32 = (octx->src[1]->type == HTP_TYPE_I32);
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for (uint32_t i = ir0; i < ir1; ++i) {
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const uint32_t i12 = fastdiv(i, &grctx->get_rows_div_ne10_ne11);
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@@ -64,7 +72,7 @@ static void get_rows_thread_f32_f32(unsigned int nth, unsigned int ith, void *da
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const uint32_t i11 = fastdiv(rem, &grctx->get_rows_div_ne10);
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const uint32_t i10 = rem - i11 * ne10;
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const uintptr_t src1_addr = octx->src1.data + i10*nb10 + i11*nb11 + i12*nb12;
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const uintptr_t src1_addr = octx->src[1]->data + i10*nb10 + i11*nb11 + i12*nb12;
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uint32_t i01 = is_i32 ? *(int32_t *)src1_addr : *(int64_t *)src1_addr;
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@@ -73,10 +81,14 @@ static void get_rows_thread_f32_f32(unsigned int nth, unsigned int ith, void *da
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continue;
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}
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const uintptr_t src0_ptr = octx->src0.data + i01*nb01 + i11*nb02 + i12*nb03;
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const uintptr_t dst_ptr = octx->dst.data + i10*nb1 + i11*nb2 + i12*nb3;
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const uintptr_t src0_ptr = octx->src[0]->data + i01*nb01 + i11*nb02 + i12*nb03;
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const uintptr_t dst_ptr = octx->dst->data + i10*nb1 + i11*nb2 + i12*nb3;
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hvx_copy_f32_uu((uint8_t *)dst_ptr, (const uint8_t *)src0_ptr, ne00);
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}
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qt = HAP_perf_qtimer_count_to_us(HAP_perf_get_qtimer_count() - qt);
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FARF(HIGH, "get-rows-f32-f32 %d/%d: %ux%ux%ux%u (%u:%u) x %ux%ux%ux%u -> %ux%ux%ux%u usec %u\n", ith, nth,
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ne00, ne01, ne02, ne03, ir0, ir1, ne10, ne11, ne12, ne13, ne0, ne1, ne2, ne3, (unsigned) qt);
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}
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int op_get_rows(struct htp_ops_context * octx) {
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@@ -84,15 +96,15 @@ int op_get_rows(struct htp_ops_context * octx) {
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const uint32_t n_threads = MIN(nr, octx->n_threads);
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if (octx->src0.type != HTP_TYPE_F32) {
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if (octx->src[0]->type != HTP_TYPE_F32) {
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return HTP_STATUS_NO_SUPPORT;
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}
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if (octx->dst.type != HTP_TYPE_F32) {
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if (octx->dst->type != HTP_TYPE_F32) {
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return HTP_STATUS_NO_SUPPORT;
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}
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if (octx->src1.type != HTP_TYPE_I32 && octx->src1.type != HTP_TYPE_I64) {
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if (octx->src[1]->type != HTP_TYPE_I32 && octx->src[1]->type != HTP_TYPE_I64) {
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return HTP_STATUS_NO_SUPPORT;
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}
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@@ -102,8 +114,8 @@ int op_get_rows(struct htp_ops_context * octx) {
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struct get_rows_context grctx;
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grctx.octx = octx;
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grctx.get_rows_div_ne10 = init_fastdiv_values(octx->src1.ne[0]);
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grctx.get_rows_div_ne10_ne11 = init_fastdiv_values(octx->src1.ne[0] * octx->src1.ne[1]);
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grctx.get_rows_div_ne10 = init_fastdiv_values(octx->src[1]->ne[0]);
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grctx.get_rows_div_ne10_ne11 = init_fastdiv_values(octx->src[1]->ne[0] * octx->src[1]->ne[1]);
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grctx.src1_nrows_per_thread = (nr + n_threads - 1) / n_threads;
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