vulkan: Support Q2_0 (#25430)
* vulkan: Support Q2_0 The backend perf tests for mat-vec-mul weren't very good at first (worse than q2_k), doubling the rows per workgroup made a big difference. * reorder * resolve merge conflict, adjust err threshold for f16->q2_0 set_rows
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@@ -6,6 +6,40 @@
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// Each iqs value maps to a 32-bit integer
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#if defined(DATA_A_Q2_0)
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void block_a_to_shmem(const uint buf_ib, const uint ib, const uint iqs) {
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const uint block_idx = ib / 2;
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const uint byte_idx = (ib & 1u) * 8u + iqs;
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const uint bits = uint(data_a[block_idx].qs[byte_idx]);
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buf_a[buf_ib].qs[iqs] = pack32(i8vec4(
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int8_t(bits & 3u),
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int8_t((bits >> 2u) & 3u),
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int8_t((bits >> 4u) & 3u),
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int8_t(bits >> 6u)));
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if (iqs == 0) {
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buf_a[buf_ib].dm = FLOAT_TYPE(data_a[block_idx].d);
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}
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}
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void block_a_to_registers(const uint reg_ib, const uint buf_ib) {
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cache_a[reg_ib].dm = buf_a[buf_ib].dm;
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[[unroll]] for (uint iqs = 0; iqs < 8; ++iqs) {
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cache_a[reg_ib].qs[iqs] = buf_a[buf_ib].qs[iqs];
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}
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}
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ACC_TYPE mmq_dot_product(const uint ib_a) {
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int32_t q_sum = 0;
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[[unroll]] for (uint iqs = 0; iqs < 8; ++iqs) {
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q_sum += dotPacked4x8EXT(cache_a[ib_a].qs[iqs], cache_b.qs[iqs]);
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}
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return ACC_TYPE(float(cache_a[ib_a].dm) * (float(q_sum) * float(cache_b.ds.x) - float(cache_b.ds.y)));
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}
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#endif
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#if defined(DATA_A_Q4_0) || defined(DATA_A_Q4_1)
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// 2-byte loads for Q4_0 blocks (18 bytes)
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// 4-byte loads for Q4_1 blocks (20 bytes)
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