CUDA: GEMM for FP32/FP16/BF16 and ne11 <= 16 (#15131)
* CUDA: GEMM for FP32/FP16/BF16 and ne11 <= 16
This commit is contained in:
+88
-22
@@ -23,13 +23,13 @@
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static __device__ __forceinline__ int ggml_cuda_movmatrix(const int x) {
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int ret = 0;
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#ifdef NEW_MMA_AVAILABLE
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#ifdef TURING_MMA_AVAILABLE
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asm("movmatrix.sync.aligned.m8n8.trans.b16 %0, %1;"
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: "=r"(ret) : "r"(x));
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#else
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GGML_UNUSED(x);
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NO_DEVICE_CODE;
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#endif // defined(NEW_MMA_AVAILABLE)
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#endif // defined(TURING_MMA_AVAILABLE)
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return ret;
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}
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@@ -167,6 +167,38 @@ namespace ggml_cuda_mma {
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}
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};
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template <int I_, int J_>
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struct tile<I_, J_, nv_bfloat162> {
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static constexpr int I = I_;
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static constexpr int J = J_;
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static constexpr int ne = I * J / WARP_SIZE;
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nv_bfloat162 x[ne] = {{0.0f, 0.0f}};
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static __device__ __forceinline__ int get_i(const int l) {
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if constexpr (I == 8 && J == 8) {
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return threadIdx.x / 4;
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} else if constexpr (I == 16 && J == 4) {
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return l * 8 + threadIdx.x / 4;
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} else if constexpr (I == 16 && J == 8) {
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return (l % 2) * 8 + threadIdx.x / 4;
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} else {
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static_assert(I == -1 && J == -1, "template specialization not implemented");
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}
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}
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static __device__ __forceinline__ int get_j(const int l) {
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if constexpr (I == 8 && J == 8) {
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return l * 4 + threadIdx.x % 4;
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} else if constexpr (I == 16 && J == 4) {
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return threadIdx.x % 4;
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} else if constexpr (I == 16 && J == 8) {
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return (l / 2) * 4 + threadIdx.x % 4;
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} else {
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static_assert(I == -1 && J == -1, "template specialization not implemented");
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}
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}
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};
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template <int I, int J>
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static __device__ __forceinline__ tile<I, J/2, half2> get_half2(const tile<I, J, float> & tile_float) {
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tile<I, J/2, half2> ret;
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@@ -209,7 +241,7 @@ namespace ggml_cuda_mma {
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template <typename T>
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static __device__ __forceinline__ void load_ldmatrix(
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tile<8, 8, T> & t, const T * __restrict__ xs0, const int stride) {
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#ifdef NEW_MMA_AVAILABLE
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#ifdef TURING_MMA_AVAILABLE
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int * xi = (int *) t.x;
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const int * xs = (const int *) xs0 + (threadIdx.x % t.I) * stride + ((threadIdx.x / t.I) * (t.J / 2)) % t.J;
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asm volatile("ldmatrix.sync.aligned.m8n8.x2.b16 {%0, %1}, [%2];"
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@@ -217,13 +249,13 @@ namespace ggml_cuda_mma {
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: "l"(xs));
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#else
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load_generic(t, xs0, stride);
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#endif // NEW_MMA_AVAILABLE
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#endif // TURING_MMA_AVAILABLE
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}
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template <typename T>
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static __device__ __forceinline__ void load_ldmatrix(
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tile<16, 4, T> & t, const T * __restrict__ xs0, const int stride) {
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#ifdef NEW_MMA_AVAILABLE
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#ifdef TURING_MMA_AVAILABLE
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int * xi = (int *) t.x;
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const int * xs = (const int *) xs0 + (threadIdx.x % t.I) * stride;
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asm volatile("ldmatrix.sync.aligned.m8n8.x2.b16 {%0, %1}, [%2];"
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@@ -232,13 +264,13 @@ namespace ggml_cuda_mma {
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#else
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load_generic(xs0, stride);
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GGML_UNUSED(t);
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#endif // NEW_MMA_AVAILABLE
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#endif // TURING_MMA_AVAILABLE
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}
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template <typename T>
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static __device__ __forceinline__ void load_ldmatrix(
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tile<16, 8, T> & t, const T * __restrict__ xs0, const int stride) {
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#if defined(NEW_MMA_AVAILABLE)
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#if defined(TURING_MMA_AVAILABLE)
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int * xi = (int * ) t.x;
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const int * xs = (const int *) xs0 + (threadIdx.x % t.I) * stride + (threadIdx.x / t.I) * (t.J / 2);
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asm volatile("ldmatrix.sync.aligned.m8n8.x4.b16 {%0, %1, %2, %3}, [%4];"
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@@ -246,13 +278,13 @@ namespace ggml_cuda_mma {
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: "l"(xs));
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#else
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load_generic(t, xs0, stride);
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#endif // NEW_MMA_AVAILABLE
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#endif // TURING_MMA_AVAILABLE
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}
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template <typename T>
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static __device__ __forceinline__ void load_ldmatrix_trans(
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tile<16, 8, T> & t, const T * __restrict__ xs0, const int stride) {
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#ifdef NEW_MMA_AVAILABLE
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#ifdef TURING_MMA_AVAILABLE
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int * xi = (int * ) t.x;
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const int * xs = (const int *) xs0 + (threadIdx.x % t.I) * stride + (threadIdx.x / t.I) * (t.J / 2);
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asm volatile("ldmatrix.sync.aligned.m8n8.x4.trans.b16 {%0, %1, %2, %3}, [%4];"
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@@ -263,12 +295,12 @@ namespace ggml_cuda_mma {
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GGML_UNUSED(xs0);
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GGML_UNUSED(stride);
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NO_DEVICE_CODE;
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#endif // NEW_MMA_AVAILABLE
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#endif // TURING_MMA_AVAILABLE
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}
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static __device__ __forceinline__ void mma(
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tile<16, 8, int> & D, const tile<16, 4, int> & A, const tile<8, 4, int> & B) {
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#ifdef NEW_MMA_AVAILABLE
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#ifdef TURING_MMA_AVAILABLE
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#if __CUDA_ARCH__ >= GGML_CUDA_CC_AMPERE
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asm("mma.sync.aligned.m16n8k16.row.col.s32.s8.s8.s32 {%0, %1, %2, %3}, {%4, %5}, {%6}, {%0, %1, %2, %3};"
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: "+r"(D.x[0]), "+r"(D.x[1]), "+r"(D.x[2]), "+r"(D.x[3])
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@@ -287,12 +319,12 @@ namespace ggml_cuda_mma {
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GGML_UNUSED(A);
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GGML_UNUSED(B);
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NO_DEVICE_CODE;
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#endif // NEW_MMA_AVAILABLE
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#endif // TURING_MMA_AVAILABLE
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}
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static __device__ __forceinline__ void mma(
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tile<16, 8, int> & D, const tile<16, 8, int> & A, const tile<8, 8, int> & B) {
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#ifdef NEW_MMA_AVAILABLE
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#ifdef TURING_MMA_AVAILABLE
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#if __CUDA_ARCH__ >= GGML_CUDA_CC_AMPERE
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asm("mma.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};"
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: "+r"(D.x[0]), "+r"(D.x[1]), "+r"(D.x[2]), "+r"(D.x[3])
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@@ -317,12 +349,12 @@ namespace ggml_cuda_mma {
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GGML_UNUSED(A);
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GGML_UNUSED(B);
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NO_DEVICE_CODE;
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#endif // NEW_MMA_AVAILABLE
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#endif // TURING_MMA_AVAILABLE
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}
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static __device__ __forceinline__ void mma(
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tile<16, 4, half2> & D, const tile<16, 8, half2> & A, const tile<8, 8, half2> & B) {
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#ifdef NEW_MMA_AVAILABLE
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#ifdef TURING_MMA_AVAILABLE
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const int * Axi = (const int *) A.x;
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const int * Bxi = (const int *) B.x;
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int * Dxi = (int *) D.x;
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@@ -344,12 +376,12 @@ namespace ggml_cuda_mma {
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GGML_UNUSED(A);
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GGML_UNUSED(B);
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NO_DEVICE_CODE;
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#endif // NEW_MMA_AVAILABLE
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#endif // TURING_MMA_AVAILABLE
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}
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static __device__ __forceinline__ void mma(
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tile<16, 8, half2> & D, const tile<16, 8, half2> & A, const tile<16, 8, half2> & B) {
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#ifdef NEW_MMA_AVAILABLE
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#ifdef TURING_MMA_AVAILABLE
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const int * Axi = (const int *) A.x;
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const int * Bxi = (const int *) B.x;
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int * Dxi = (int *) D.x;
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@@ -380,12 +412,29 @@ namespace ggml_cuda_mma {
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GGML_UNUSED(A);
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GGML_UNUSED(B);
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NO_DEVICE_CODE;
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#endif // NEW_MMA_AVAILABLE
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#endif // TURING_MMA_AVAILABLE
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}
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static __device__ __forceinline__ void mma(
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tile<16, 8, float> & D, const tile<16, 8, float> & A, const tile<8, 8, float> & B) {
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#ifdef AMPERE_MMA_AVAILABLE
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const int * Axi = (const int *) A.x;
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const int * Bxi = (const int *) B.x;
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int * Dxi = (int *) D.x;
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asm("mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};"
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: "+r"(Dxi[0]), "+r"(Dxi[1]), "+r"(Dxi[2]), "+r"(Dxi[3])
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: "r"(Axi[0]), "r"(Axi[1]), "r"(Axi[2]), "r"(Axi[3]), "r"(Bxi[0]), "r"(Bxi[1]));
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#else
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GGML_UNUSED(D);
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GGML_UNUSED(A);
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GGML_UNUSED(B);
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NO_DEVICE_CODE;
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#endif // AMPERE_MMA_AVAILABLE
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}
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static __device__ __forceinline__ void mma(
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tile<16, 8, float> & D, const tile<16, 8, half2> & A, const tile<8, 8, half2> & B) {
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#ifdef NEW_MMA_AVAILABLE
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#ifdef TURING_MMA_AVAILABLE
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const int * Axi = (const int *) A.x;
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const int * Bxi = (const int *) B.x;
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int * Dxi = (int *) D.x;
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@@ -407,12 +456,29 @@ namespace ggml_cuda_mma {
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GGML_UNUSED(A);
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GGML_UNUSED(B);
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NO_DEVICE_CODE;
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#endif // NEW_MMA_AVAILABLE
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#endif // TURING_MMA_AVAILABLE
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}
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static __device__ __forceinline__ void mma(
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tile<16, 8, float> & D, const tile<16, 8, nv_bfloat162> & A, const tile<8, 8, nv_bfloat162> & B) {
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#ifdef AMPERE_MMA_AVAILABLE
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const int * Axi = (const int *) A.x;
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const int * Bxi = (const int *) B.x;
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int * Dxi = (int *) D.x;
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asm("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};"
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: "+r"(Dxi[0]), "+r"(Dxi[1]), "+r"(Dxi[2]), "+r"(Dxi[3])
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: "r"(Axi[0]), "r"(Axi[1]), "r"(Axi[2]), "r"(Axi[3]), "r"(Bxi[0]), "r"(Bxi[1]));
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#else
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GGML_UNUSED(D);
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GGML_UNUSED(A);
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GGML_UNUSED(B);
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NO_DEVICE_CODE;
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#endif // AMPERE_MMA_AVAILABLE
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}
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static __device__ __forceinline__ void mma(
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tile<16, 16, float> & D, const tile<16, 8, half2> & A, const tile<16, 8, half2> & B) {
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#ifdef NEW_MMA_AVAILABLE
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#ifdef TURING_MMA_AVAILABLE
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const int * Axi = (const int *) A.x;
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const int * Bxi = (const int *) B.x;
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int * Dxi = (int *) D.x;
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@@ -443,7 +509,7 @@ namespace ggml_cuda_mma {
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GGML_UNUSED(A);
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GGML_UNUSED(B);
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NO_DEVICE_CODE;
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#endif // NEW_MMA_AVAILABLE
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#endif // TURING_MMA_AVAILABLE
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}
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static __device__ __forceinline__ void mma(
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