ggml : recurrent state rollback for ggml_ssm_scan (#26623)
* Initial changes for Recurrent state rollback for nemotron for cpu and cuda * Removing CPU RS rollback. Will enable it in subsequent PRs * addition of test case * Removing assert and calling runtime API to check if op is supported * removing extra API and updating the call sites for K * replace static cuda detection to runtime fused_op api * address review comments and fallback when SSM rollback not supprted * Adding changes for supporting RS-rollback in CPU. Also added test-backend-ops for cpu and cuda * removing memory manipulation as rs rollback is now supported in CPU * removing the static probe which is not needed now * correcting the format * address review comments * enabling test for all the backends, unsupported backends will fallback to CPU * Apply suggestions from code review Co-authored-by: Georgi Gerganov <ggerganov@gmail.com> * choose different graph based on the result of fused_ssm_op is supported or not and also handled memory->n_rs_seq >1 case incase of op is not supported * Support K > 1 in ssm_scan for all backends * Fix CI Issues --------- Co-authored-by: Georgi Gerganov <ggerganov@gmail.com> Co-authored-by: Gaurav Garg <gaugarg@nvidia.com>
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co-authored by
Georgi Gerganov
Gaurav Garg
parent
4c1a0af40d
commit
1692f9e50b
@@ -1376,9 +1376,10 @@ bool ggml_metal_device_supports_op(ggml_metal_device_t dev, const struct ggml_te
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ggml_is_contiguous_rows(op->src[1]) &&
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ggml_is_contiguous_rows(op->src[2]) &&
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ggml_is_contiguous_rows(op->src[3]);
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case GGML_OP_SSM_CONV:
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case GGML_OP_SSM_SCAN:
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return has_simdgroup_reduction;
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case GGML_OP_SSM_CONV:
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return has_simdgroup_reduction;
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case GGML_OP_RWKV_WKV6:
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case GGML_OP_RWKV_WKV7:
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return true;
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@@ -880,6 +880,7 @@ typedef struct {
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int64_t n_group;
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int64_t n_seq_tokens;
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int64_t n_seqs;
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int64_t K;
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uint64_t s_off;
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uint64_t nb00;
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uint64_t nb01;
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@@ -1710,6 +1710,10 @@ int ggml_metal_op_ssm_scan(ggml_metal_op_t ctx, int idx) {
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const int64_t n_group = ne41;
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const int64_t n_seq_tokens = ne12;
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const int64_t n_seqs = ne13;
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const int64_t K = ggml_get_op_params_i32(op, 0);
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GGML_ASSERT(K >= 1);
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GGML_ASSERT(ggml_nelements(op->src[1]) + K*d_state*d_inner*n_head*n_seqs == ggml_nelements(op));
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ggml_metal_kargs_ssm_scan args = {
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/*.d_state =*/ d_state,
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@@ -1718,6 +1722,7 @@ int ggml_metal_op_ssm_scan(ggml_metal_op_t ctx, int idx) {
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/*.n_group =*/ n_group,
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/*.n_seq_tokens =*/ n_seq_tokens,
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/*.n_seqs =*/ n_seqs,
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/*.K =*/ K,
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/*.s_off =*/ ggml_nelements(op->src[1]) * sizeof(float),
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/*.nb00 =*/ nb00,
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/*.nb01 =*/ nb01,
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@@ -2429,6 +2429,8 @@ kernel void kernel_ssm_scan_f32(
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const int32_t nh = args.n_head;
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const int32_t ng = args.n_group;
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const int32_t n_t = args.n_seq_tokens;
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const int32_t n_s = args.n_seqs;
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const int32_t K = args.K;
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const int32_t s_off = args.s_off;
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@@ -2487,6 +2489,12 @@ kernel void kernel_ssm_scan_f32(
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// recurse
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s0 = s;
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const int32_t slot = n_t - 1 - (i2 + t);
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if (slot > 0 && slot < K) {
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device float * s_snapshot = (device float *) ((device char *) s_buff + (int64_t) slot*n_s*args.nb03);
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s_snapshot[i] = s;
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}
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B += args.ns42;
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C += args.ns52;
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}
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