metal: SSM kernel improvements (#17876)
* feat: Add a batched version of ssm_conv This was done using Claude Code. It found a number of optimizations around how the threads were organized, resulting in a huge performance boost! Branch: Mamba2SSD Signed-off-by: Gabe Goodhart <ghart@us.ibm.com> * feat: Optimized SSM_SCAN kernel for metal This used Claude Code and resulted in a modest performance improvement while maintaining correctness. Branch: Mamba2SSD Signed-off-by: Gabe Goodhart <ghart@us.ibm.com> * test: Add test-backend-ops perf tests for SSM_CONV Branch: SSMKernelImprovements Signed-off-by: Gabe Goodhart <ghart@us.ibm.com> * test: Real representitive tests for SSM_CONV Branch: SSMKernelImprovements Signed-off-by: Gabe Goodhart <ghart@us.ibm.com> * refactor: Use function constant for ssm_conv batch size Branch: SSMKernelImprovements Signed-off-by: Gabe Goodhart <ghart@us.ibm.com> * test: backend op tests for ssm_scan from granite4 1b-h Branch: SSMKernelImprovements Signed-off-by: Gabe Goodhart <ghart@us.ibm.com> * style: remove commented out templates Branch: SSMKernelImprovements Signed-off-by: Gabe Goodhart <ghart@us.ibm.com> * feat: float4 version of ssm_conv_batched Branch: SSMKernelImprovements Signed-off-by: Gabe Goodhart <ghart@us.ibm.com> * fix: Add missing ggml_metal_cv_free Signed-off-by: Gabe Goodhart <ghart@us.ibm.com> Co-authored-by: Georgi Gerganov <ggerganov@gmail.com> --------- Signed-off-by: Gabe Goodhart <ghart@us.ibm.com> Co-authored-by: Georgi Gerganov <ggerganov@gmail.com>
This commit is contained in:
Gabe Goodhart
co-authored by
Georgi Gerganov
Georgi Gerganov
parent
b63509262a
commit
086a63e3a5
@@ -2343,7 +2343,102 @@ kernel void kernel_ssm_conv_f32_f32_4(
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x[0] = sumf;
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}
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constant short FC_ssm_conv_bs [[function_constant(FC_SSM_CONV + 0)]];
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// Batched version: each threadgroup processes multiple tokens for better efficiency
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// Thread layout: each thread handles one token, threadgroup covers BATCH_SIZE tokens
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kernel void kernel_ssm_conv_f32_f32_batched(
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constant ggml_metal_kargs_ssm_conv & args,
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device const void * src0,
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device const void * src1,
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device float * dst,
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uint3 tgpig[[threadgroup_position_in_grid]],
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uint3 tpitg[[thread_position_in_threadgroup]],
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uint3 ntg[[threads_per_threadgroup]]) {
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// tgpig.x = row index (ir)
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// tgpig.y = batch of tokens (i2_base / BATCH_SIZE)
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// tgpig.z = sequence index (i3)
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// tpitg.x = thread within batch (0..BATCH_SIZE-1)
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const short BATCH_SIZE = FC_ssm_conv_bs;
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const int64_t ir = tgpig.x;
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const int64_t i2_base = tgpig.y * BATCH_SIZE;
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const int64_t i3 = tgpig.z;
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const int64_t i2_off = tpitg.x;
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const int64_t i2 = i2_base + i2_off;
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const int64_t nc = args.ne10; // conv kernel size (typically 4)
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const int64_t n_t = args.ne1; // number of tokens
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// Bounds check for partial batches at the end
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if (i2 >= n_t) {
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return;
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}
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// Load conv weights (shared across all tokens for this row)
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device const float * c = (device const float *) ((device const char *) src1 + ir*args.nb11);
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// Load source for this specific token
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device const float * s = (device const float *) ((device const char *) src0 + ir*args.nb01 + i2*args.nb00 + i3*args.nb02);
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// Output location for this token
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device float * x = (device float *) ((device char *) dst + ir*args.nb0 + i2*args.nb1 + i3*args.nb2);
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float sumf = 0.0f;
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for (int64_t i0 = 0; i0 < nc; ++i0) {
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sumf += s[i0] * c[i0];
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}
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x[0] = sumf;
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}
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kernel void kernel_ssm_conv_f32_f32_batched_4(
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constant ggml_metal_kargs_ssm_conv & args,
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device const void * src0,
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device const void * src1,
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device float * dst,
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uint3 tgpig[[threadgroup_position_in_grid]],
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uint3 tpitg[[thread_position_in_threadgroup]],
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uint3 ntg[[threads_per_threadgroup]]) {
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// tgpig.x = row index (ir)
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// tgpig.y = batch of tokens (i2_base / BATCH_SIZE)
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// tgpig.z = sequence index (i3)
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// tpitg.x = thread within batch (0..BATCH_SIZE-1)
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const short BATCH_SIZE = FC_ssm_conv_bs;
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const int64_t ir = tgpig.x;
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const int64_t i2_base = tgpig.y * BATCH_SIZE;
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const int64_t i3 = tgpig.z;
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const int64_t i2_off = tpitg.x;
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const int64_t i2 = i2_base + i2_off;
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const int64_t nc = args.ne10; // conv kernel size (typically 4)
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const int64_t n_t = args.ne1; // number of tokens
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// Bounds check for partial batches at the end
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if (i2 >= n_t) {
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return;
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}
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// Load conv weights (shared across all tokens for this row)
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device const float4 * c = (device const float4 *) ((device const char *) src1 + ir*args.nb11);
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// Load source for this specific token
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device const float4 * s = (device const float4 *) ((device const char *) src0 + ir*args.nb01 + i2*args.nb00 + i3*args.nb02);
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// Output location for this token
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device float * x = (device float *) ((device char *) dst + ir*args.nb0 + i2*args.nb1 + i3*args.nb2);
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float sumf = 0.0f;
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for (int64_t i0 = 0; i0 < nc/4; ++i0) {
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sumf += dot(s[i0], c[i0]);
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}
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x[0] = sumf;
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}
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// ref: ggml.c:ggml_compute_forward_ssm_scan_f32, Mamba-2 part
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// Optimized version: reduces redundant memory loads by having one thread load shared values
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kernel void kernel_ssm_scan_f32(
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constant ggml_metal_kargs_ssm_scan & args,
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device const void * src0,
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@@ -2363,7 +2458,15 @@ kernel void kernel_ssm_scan_f32(
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uint3 tgpg[[threadgroups_per_grid]]) {
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constexpr short NW = N_SIMDWIDTH;
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shared[tpitg.x] = 0.0f;
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// Shared memory layout:
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// [0..sgptg*NW-1]: partial sums for reduction (existing)
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// [sgptg*NW..sgptg*NW+sgptg-1]: pre-computed x_dt values for each token in batch
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// [sgptg*NW+sgptg..sgptg*NW+2*sgptg-1]: pre-computed dA values for each token in batch
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threadgroup float * shared_sums = shared;
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threadgroup float * shared_x_dt = shared + sgptg * NW;
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threadgroup float * shared_dA = shared + sgptg * NW + sgptg;
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shared_sums[tpitg.x] = 0.0f;
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const int32_t i0 = tpitg.x;
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const int32_t i1 = tgpig.x;
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@@ -2403,32 +2506,47 @@ kernel void kernel_ssm_scan_f32(
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for (int i2 = 0; i2 < n_t; i2 += sgptg) {
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threadgroup_barrier(mem_flags::mem_threadgroup);
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for (int t = 0; t < sgptg && i2 + t < n_t; t++) {
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const float dt0 = dt[0];
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// Pre-compute x_dt and dA for this batch of tokens
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// Only first sgptg threads do the loads and expensive math
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if (i0 < sgptg && i2 + i0 < n_t) {
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// ns12 and ns21 are element strides (nb12/nb10, nb21/nb20)
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device const float * x_t = x + i0 * args.ns12;
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device const float * dt_t = dt + i0 * args.ns21;
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const float dt0 = dt_t[0];
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const float dtsp = dt0 <= 20.0f ? log(1.0f + exp(dt0)) : dt0;
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const float x_dt = x[0] * dtsp;
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const float dA = exp(dtsp * A0);
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shared_x_dt[i0] = x_t[0] * dtsp;
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shared_dA[i0] = dtsp; // Store dtsp, compute exp(dtsp * A0) per-thread since A0 varies
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}
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threadgroup_barrier(mem_flags::mem_threadgroup);
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for (int t = 0; t < sgptg && i2 + t < n_t; t++) {
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const float x_dt = shared_x_dt[t];
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const float dA = exp(shared_dA[t] * A0);
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s = (s0 * dA) + (B[i0] * x_dt);
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const float sumf = simd_sum(s * C[i0]);
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if (tiisg == 0) {
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shared[t*NW + sgitg] = sumf;
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shared_sums[t*NW + sgitg] = sumf;
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}
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// recurse
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s0 = s;
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x += args.ns12;
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dt += args.ns21;
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B += args.ns42;
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C += args.ns52;
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}
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// Advance pointers for next batch
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x += sgptg * args.ns12;
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dt += sgptg * args.ns21;
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threadgroup_barrier(mem_flags::mem_threadgroup);
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const float sumf = simd_sum(shared[sgitg*NW + tiisg]);
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const float sumf = simd_sum(shared_sums[sgitg*NW + tiisg]);
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if (tiisg == 0 && i2 + sgitg < n_t) {
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y[sgitg*nh*nr] = sumf;
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