Add flash attention MMA / Tiles to support MiMo-V2.5 (#22812)
* mimo-v2.5: add flash attention mma/tiles for for d_kq=192 d_v=128 * mimo-v2.5: follow (256, 256) fattn templates * mimo-v2.5: cleanup comments * mimo-v2.5: further comment cleanup * mimo-v2.5: address PR feedback fix GQA handling check for other dangling 320/576 carveouts and mirror them for 192 Add to backend ops test so new paths are covered
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@@ -139,6 +139,22 @@ static void ggml_cuda_flash_attn_ext_mma_f16(ggml_backend_cuda_context & ctx, gg
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GGML_ASSERT(V->ne[0] == 128);
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ggml_cuda_flash_attn_ext_mma_f16_switch_ncols2<128, 128>(ctx, dst);
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break;
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case 192: {
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// MiMo-V2.5 / V2.5-Pro / V2-Flash: gqa_ratio is 8 (SWA) or 16 (full attn)
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GGML_ASSERT(V->ne[0] == 128);
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float max_bias = 0.0f;
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memcpy(&max_bias, (const float *) KQV->op_params + 1, sizeof(float));
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const bool use_gqa_opt = mask && max_bias == 0.0f;
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GGML_ASSERT(use_gqa_opt);
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GGML_ASSERT(Q->ne[2] % K->ne[2] == 0);
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const int gqa_ratio = Q->ne[2] / K->ne[2];
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if (gqa_ratio % 16 == 0) {
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ggml_cuda_flash_attn_ext_mma_f16_switch_ncols1<192, 128, 16>(ctx, dst);
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} else {
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GGML_ASSERT(gqa_ratio % 8 == 0);
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ggml_cuda_flash_attn_ext_mma_f16_switch_ncols1<192, 128, 8>(ctx, dst);
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}
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} break;
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case 256:
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GGML_ASSERT(V->ne[0] == 256);
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ggml_cuda_flash_attn_ext_mma_f16_switch_ncols2<256, 256>(ctx, dst);
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@@ -368,6 +384,14 @@ static best_fattn_kernel ggml_cuda_get_best_fattn_kernel(const int device, const
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return BEST_FATTN_KERNEL_NONE;
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}
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break;
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case 192:
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if (V->ne[0] != 128 || !gqa_opt_applies) {
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return BEST_FATTN_KERNEL_NONE;
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}
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if (gqa_ratio % 8 != 0) {
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return BEST_FATTN_KERNEL_NONE;
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}
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break;
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case 320:
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if (V->ne[0] != 256 || !gqa_opt_applies) {
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return BEST_FATTN_KERNEL_NONE;
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@@ -425,7 +449,8 @@ static best_fattn_kernel ggml_cuda_get_best_fattn_kernel(const int device, const
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}
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// For small batch sizes the vector kernel may be preferable over the kernels optimized for large batch sizes:
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const bool can_use_vector_kernel = Q->ne[0] <= 256 && Q->ne[0] % 64 == 0 && K->ne[1] % FATTN_KQ_STRIDE == 0;
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// 192 satisfies % 64 == 0 but has no vec instance (DKQ != DV); force it onto the MMA path.
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const bool can_use_vector_kernel = Q->ne[0] <= 256 && Q->ne[0] % 64 == 0 && Q->ne[0] != 192 && K->ne[1] % FATTN_KQ_STRIDE == 0;
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// If Turing tensor cores are available, use them:
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if (turing_mma_available(cc) && Q->ne[0] != 40 && Q->ne[0] != 72) {
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@@ -454,7 +479,7 @@ static best_fattn_kernel ggml_cuda_get_best_fattn_kernel(const int device, const
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if (volta_mma_available(cc) && Q->ne[0] != 40 && Q->ne[0] != 72) {
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int gqa_ratio_eff = 1;
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const int ncols2_max = Q->ne[0] == 576 ? 16 : 8;
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const int ncols2_max = (Q->ne[0] == 576 || Q->ne[0] == 192) ? 16 : 8;
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while (gqa_ratio % (2*gqa_ratio_eff) == 0 && gqa_ratio_eff < ncols2_max) {
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gqa_ratio_eff *= 2;
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}
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@@ -468,7 +493,7 @@ static best_fattn_kernel ggml_cuda_get_best_fattn_kernel(const int device, const
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}
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// Use the WMMA kernel if possible:
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if (ggml_cuda_should_use_wmma_fattn(cc) && K->ne[1] % FATTN_KQ_STRIDE == 0 && Q->ne[0] != 40 && Q->ne[0] != 72 && Q->ne[0] != 512 && Q->ne[0] != 576) {
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if (ggml_cuda_should_use_wmma_fattn(cc) && K->ne[1] % FATTN_KQ_STRIDE == 0 && Q->ne[0] != 40 && Q->ne[0] != 72 && Q->ne[0] != 192 && Q->ne[0] != 512 && Q->ne[0] != 576) {
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if (can_use_vector_kernel && Q->ne[1] <= 2) {
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return BEST_FATTN_KERNEL_VEC;
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}
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@@ -501,7 +526,7 @@ static best_fattn_kernel ggml_cuda_get_best_fattn_kernel(const int device, const
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}
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// Use MFMA flash attention for CDNA (MI100+):
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if (amd_mfma_available(cc) && Q->ne[0] != 40 && Q->ne[0] != 72 && Q->ne[0] != 256 && Q->ne[0] != 512 && Q->ne[0] != 576) {
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if (amd_mfma_available(cc) && Q->ne[0] != 40 && Q->ne[0] != 72 && Q->ne[0] != 192 && Q->ne[0] != 256 && Q->ne[0] != 512 && Q->ne[0] != 576) {
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const int64_t eff_nq = Q->ne[1] * (gqa_opt_applies ? gqa_ratio : 1);
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// MMA vs tile crossover benchmarked on MI300X @ d32768:
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// hsk=64 (gqa=4): MMA wins at eff >= 128 (+11%)
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